1. Field of the Invention
The disclosure generally relates to a duty cycle corrector, and more particularly, relates to a duty cycle corrector for supplying a stable output clock.
2. Description of the Related Art
A duty cycle corrector (DCC) is used to supply an output clock having a duty cycle of 50%. This is widely applied to circuits which require rising edges and falling edges of a clock, such as DDR SDRAM (Double Date Rate Synchronous Dynamic Random Access Memory), Double-Sampling ADC (Double Sampling Analog-to-Digital Converter), DLL (Delay Locked Loop), and PLL (Phase Locked Loop).
Traditionally, a duty cycle corrector has the following disadvantages: (1) the output clock is unstable due to variations in manufacturing processes; and (2) if an input clock does not have a duty cycle of 50%, there will be a short current from a work voltage to a ground voltage, thereby increasing power consumption.